1. Field of the Invention
The present invention relates to substrate biasing provided on a microprocessor die to reduce sub-threshold leakage, and more particularly to an apparatus and method for selective substrate biasing for a functional block on the microprocessor to reduce power consumption and to minimize noise on device substrates within the functional block.
2. Description of the Related Art
Complementary Metal-Oxide Semiconductor (CMOS) circuitry dissipates less power and is more dense than other types of integrated circuit (IC) technologies so that CMOS technology has become the dominant style of digital circuit design for integrated circuits. CMOS circuits use a combination of N channel (NMOS) and P channel (PMOS) devices each having a threshold gate-to-source voltage based on design, scale, materials and process. As IC design and fabrication techniques continue to evolve, operating voltages and device size have each scaled downward. The 65 nanometer (65 nm) process is an advanced lithographic process used for volume CMOS semiconductor fabrication and is particularly advantageous for Very Large Scale Integrated (VLSI) circuits, such as microprocessors and the like. As device size and voltage levels have decreased, the channel lengths and oxide thicknesses of each device have also decreased. Manufacturers have also switched to gate materials causing lower voltage thresholds which have further led to increased sub-threshold leakage current. Sub-threshold leakage current is the current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage of the CMOS device. In many conventional circuits the substrate interface, also referred to as the well or bulk tie, of each CMOS device is coupled to a corresponding one of the power rails (e.g., PMOS bulk tied to VDD and NMOS bulk tied to VSS). In such conventional configurations the sub-threshold leakage current may account for nearly 30% or more of total power consumption in the dynamic environment (e.g., during normal operation).
It is often desired to operate an IC in a low power mode (e.g., sleep or hibernation mode) and reduce power consumption as much as possible. A bias generator or charge pump is used to bias device substrates to a voltage level other than the supply voltages during low power mode. The bias generator may be provided on the chip die or provided off-chip. In either case, the bias generator raises the bulk tie of PMOS devices above VDD and lowers the voltage of the bulk tie of NMOS devices below VSS. Such substrate biasing significantly reduces the sub-threshold leakage current during low power mode thereby conserving a substantial amount of power. In a large scale device, however, such as a microprocessor or the like, it is not always desired to place the entire device in the low power state. It is desired to reduce sub-threshold leakage current in at least a portion of a microprocessor when that portion is not in use.